Providing doping at preselected locations in a semiconductor substrate is employed in numerous types of integrated circuit structures for various reasons. For instance, it might be desirable to provide doping in the channel region of a depletion-mode MOSFET, to provide field doping beneath field isolation regions between devices, to provide doping to function as one electrode of a capacitor of a one-device memory cell, and the like. For convenience, the description of the invention, as well as the problems of the prior art, will be discussed hereinbelow primarily with respect to providing field doping beneath field isolation regions. However, it is understood that the process of the present invention is applicable for providing doping at preselected locations of an integrated circuit in general and is not limited to doping beneath field isolations. Furthermore, the process is applicable to various types of integrated circuits such as MOSFET, bipolar, or MESFET integrated circuits.
An extremely important aspect of integrated circuits is the means provided for electrically isolating adjacent devices on the same substrate. The fabrication step or steps that produce the isolation affects the spacing between devices (i.e., the device packing density) as well as the electrical characteristics of the device. The presence of doping beneath the isolation regions is often referred to as a "parasitic channel stopper" doping and is important for eliminating unwanted conduction due to inversion under the field isolation when lightly doped substrates are employed. The use of lightly doped substrates has been practiced in order to reduce diffused line capacitance which degrades performance as well as reducing hot electron effects which degrade reliability. Along with the channel stopper doping under the field isolation, there is also normally present channel doping in the device areas in order to adjust the gate threshold voltage to an acceptable operating level. One technique employed to provide the channel stopper or "field" doping is to use an extra masking step. This approach has been described by R. J. Whittier, "Semiconductor Memories: The Impact and Momentum of Current Technology", IEEE Electro 76 Meeting Tech. Digest, Session 33, p. 2, Boston, May 11, 1976. The resultant isolation structure, which is shown in FIG. 1, provides a doping region which is not self-aligned to the isolation material (i.e., silicon dioxide). Consequently this technique suffers from the disadvantage of requiring additional area, thus reducing the device packing density, as well as the additional masking operation. The resist regions used to define the isolation regions are located over the isolation regions rather than over the device areas. This technique is sometimes referred to as nonrecessed or "planar" isolation.
In the aforementioned article by Whittier, another isolation technique is described which provides self-alignment of the field doping to the field isolation. This technique is sometimes referred to as selective or local or semirecessed oxidation and is described by P. Richman, U.S. Pat. No. 3,751,722, Aug. 7, 1973, and by E. Kooi, U.S. Pat. No. 3,752,711, Aug. 14, 1973. In order to form a recessed isolation oxide with a self-aligned channel stopper, an oxidation barrier layer such as silicon nitride is delineated in the device regions. Thin silicon dioxide layers may be provided on either side of the silicon nitride layer to aid in its delineation and to prevent damage to the underlying silicon substrate. The resist pattern used to define the device regions also serves as the implantation mask. The resist regions are located over the future device areas.
The semirecessed oxide isolation structure is illustrated in FIG. 2. It has a number of attractive features including self-alignment of the field doping and field isolation, the use of only one masking step, and improved planarity. However, this procedure still presents a number of disadvantages. For instance, the presence of the oxidation barrier layer such as the nitride over the device regions may cause strain and thus permanently damage the device regions during the thermal oxidation required to form the field isolation. In addition, the device area is undesirably reduced and the field isolation area undesirably increased by lateral oxidation or what is commonly termed in the art as the "Bird's Beak Effect" and described by E. Bassous, H.N. Yu, and V. Maniscalco, "The Formation of Bird's Beak in Si Structure with Recessed SiO.sub.2 ", Extended Abstracts, pp. 457-458, ECS Fall Meeting, Dallas, Oct. 5-10, 1975. Moreover, the procedure requires additional layers of silicon dioxide (substrate protection), silicon nitride (oxidation barrier layer), and silicon dioxide (defining oxide layer) in order to protect and define the device regions. Furthermore, the removal of the defining oxide layer affects the thickness of the recessed oxide or its lateral extent, particularly when a relatively thick oxide layer is required as in a fully-recessed oxide isolation region formed as described, for example, by R. H. Dennard, V. L. Rideout, and E. J. Walker, U.S. Pat. No. 3,899,363, Aug. 12, 1975.
In comparing the planar isolation of FIG. 1 with the recessed isolation of FIG. 2, the self-aligned field doping of the recessed oxide technique occurs because the resist masking pattern that defines the field and device regions is located over the device regions and can thereby also serve as an implantation mask to prevent the field doping from entering the device regions. The field oxide is formed locally by a thermal oxidation. With the planar isolation technique, the resist masking pattern is located over the field regions, and device areas are revealed by locally etching away silicon dioxide in the device areas. Accordingly, it is an object of the present invention to provide the simplicity of planar isolation (i.e., no silicon nitride or Bird's Beak problems) but with a self-aligned field doping in one lithographic pattern delineation step.
One approach to the problem of providing planar isolation with field doping is that of R. H. Dennard and V. L. Rideout, "N-Channel MOSFETS having a Common Field-Channel Implant", IBM Tech. Bulletin, Vol. 18, pp. 1289-91. September 1975, in which a common field isolation and device channel doping is provided in a single step. Although attractively simple, this process has the disadvantage that the channel doping controls the field doping. Often one would like the field doping to exceed the channel doping by a factor of five to ten times to enhance the isolation protection in the field region. Accordingly, it is a further object of the present invention to decouple the field isolation doping from the device channel doping for the purpose of improving the field isolation characteristic.
It is important to employ as few masking steps as possible since the lithographic masking steps involved in preparing integrated circuits are among the most critical. The lithographic masking steps require high precision and registration and extreme care in execution. Each additional lithographic masking step in a process introduces possible surface damage due to mask defects, and increases mask-to-mask registration problems that decrease the processing yield and accordingly significantly increases the fabrication cost. Although other factors affect the yield and cost, such as, for example, the number of high temperature heat treatments, a basic objective in FET integrated circuit fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of desired device structures. Consequently, a further object of the present invention is to provide a process wherein the incorporation of the doping beneath the preselected isolation regions and the fabrication of the isolation regions requires only a single lithographic masking operation.